System Control and Status Registers (CSRs)

The THEJAS32 SoC includes a set of control and status registers (CSRs) that allow software to control and monitor the processor’s behavior. The CSRs provide access to various system configuration, status, and control registers, including:

• Machine status registers (mstatus, misa, etc.)

• Machine trap handling registers (mtvec, mcause, mie, etc.)

• Machine memory management registers (satp, etc.)

Refer to the RISC-V specification for a complete list of CSRs supported by the RV32IM architecture.

Exceptions and Interrupts

The RV32IM architecture supports exceptions and interrupts, which are used to handle exceptional events and asynchronous events, respectively. Exceptions can occur due to events like illegal instructions, divide-by-zero, and page faults, while interrupts are typically generated by external devices or timers.

When an exception or interrupt occurs, the CPU core saves the current context, including the program counter and registers, and transfers control to the exception or interrupt handler. After handling the exception or interrupt, the core resumes execution from the saved context.